1. Technical Field
The present invention relates to an apparatus for reproducing data from a data recording medium and a method thereof. More particularly, it relates to an apparatus and a method for reproducing data in which rates of convergence for errors in amplitude and frequency of a signal read from the data recording medium are dynamically controlled to remove offset in the read signal.
2. Description of Related Art
Typical examples of recording media for storing data, such as documents, images, and sound are a magnetic disk HDD (Hard Disk Drive), a DVD (Digital Video Disk or Digital Versatile Disk), an MO (Magneto-optic Disk), a CD (Compact Disk), and an LD (Laser Disk), or the like. FIG. 5(a) shows an outline of a data reproduction apparatus 70 for reproducing digital data from a medium 72. A read signal read from the medium 72 is digitized with a level determining unit 74 to be converted to a bit string (binary data) composed of 0""s and 1""s. The binary data is sent to a decoder 76 to be reproduced. For example, as shown in FIG. 5(b), synchronization marks (Sync) for synchronization, address marks (AM), and data (DATA) are recorded in the medium 72.
FIG. 5(c) shows an example of the structure of the level determining unit 74. An automatic gain control (AGC) circuit 82 maintains a constant amplitude of a read signal read from medium 72. An AGC output signal V(t) of constant amplitude is sent to a zero cross detector 84. For example, the zero cross detector 84 defines a threshold level (slicing level) Vr, as shown in FIG. 6, based on the maximum and minimum values of the read signal V(t) to detect intersections (Pz0-1,2,3,4) of the output signal V(t) and the slicing level Vr. Subsequently, the zero cross detector 84 sends a detection signal Z0 indicative of the intersections to a binarization circuit 86. The binarization circuit 86 defines time cells having a period determined by the frequency of the output signal V(t) detected by a phase-locked loop circuit (PLL) 88 to generate binary data based on presence or absence of the intersections Pz0-1,2,3,4 (Time Tz0-1,2,3,4) in each time cell.
The AGC circuit 82 keeps the amplitude of the output signal V(t) at a predetermined amplitude A0 regardless of fluctuations of frequency in an input signal. The amplitude is controlled as a function of voltage xcex1Vca (xcex1 is a set value), which is proportional to an error or difference between the amplitude of the output signal V(t) and the predetermined amplitude A0. xcex1 can be adjusted by controlling the gain of an amplifier to amplify the voltage Vca. xcex1 is hereinafter referred to as a xe2x80x9cfeedback gainxe2x80x9d of the AGC circuit 82.
PLL 88 defines time cells having a period determined by the frequency of the output signal V(t). The period is controlled as a function of voltage xcex2Vcp (xcex2 is a set value), which is proportional to an error or difference between the frequency of the output signal V(t) and the frequency of the time cells (a reciprocal of the cycle). xcex2 can be adjusted by controlling the gain of an amplifier to amplify the voltage Vcp. xcex2 is hereinafter referred to as a xe2x80x9cfeedback gainxe2x80x9d of PLL 88.
When both feedback gains xcex1 and xcex2 of the AGC circuit 82 and PLL 88 are set high, sensitivity to errors becomes higher because of high amplification of the errors, so that the rate of convergence of the errors becomes faster. On the contrary, when xcex1 and xcex2 are set low, the sensitivity to the errors becomes lower because of low amplification, so that the convergence rates become slower.
At early stages of operation of the AGC circuit 82 and PLL 88, feedback gains a and b are set high to converge the errors rapidly. When operation is stabilized by the convergence of the errors, the feedback gains a and b are lowered to prevent malfunction caused by disturbance. Signals AGC-H/L and PLL-H/L outputted from a timer circuit 80 respectively switch the feedback gains a and b of the AGC circuit 82 and PLL 88. The timer circuit 80 gives an instruction to operate at a high feedback gain during the early stages of the operation. After a lapse of a predetermined time, the timer circuit 80 gives an instruction to operate at a low feedback gain. The rate of error convergence is proportional to the feedback gains.
For example, as a dot-dash-line in FIG. 7(a) shows, a feedback gain is initially set to High to rapidly converge the error and then the feedback gain is set to Low. However, when noise is originated immediately before switching the setting of the feedback gain from High to Low, as a solid line in FIG. 7(a) shows, the error is caused to converge slowly due to a low feedback gain. There is a possibility that the convergence of the error is not completed when an address mark (AM) is read due to the slow rate of convergence. Unless the convergence of the error has been completed, data may be unable to be read.
As shown in FIG. 7(b), there may be used a data recording format with repeated recording of synchronization and address marks to allow for the convergence time in the existence of noise. This data recording format wastes recording capacity because of overlapped recording of synchronization and address marks.
When an MR (Magneto resistive) head is used for a read/write head of hard disk, heat generation caused by a touch of the MR head on the surface of a magnetic disk changes magneto resistance. The changes in magneto resistance cause noise called xe2x80x9cThermal Asperityxe2x80x9d. Graphed as a dotted line in FIG. 2(a), thermal asperity can be approximated by exe2x88x92t/xcfx84 (xcfx84 is a constant). A shift is caused by the thermal asperity at an intersection of the output signal V(t) and the slicing level Vr.
Since thermal asperity lasts until the heated MR head has returned to its original temperature, it takes a long time to converge the shift. As shown in FIG. 5(c), the level determining unit 74 generates an error correcting code (ECC) at the time of binarizing the read signal to send it to the decoder 76. The error correction circuit 78 in the decoder 76 corrects errors in binary data using ECC. The error convergence time often, however, may be so long that ECC cannot work and thus data errors cannot be corrected using ECC.
It is an object of the present invention to rapidly correct offset of a read signal which may cause data errors.
A data reproduction apparatus according to the present invention includes a differentiating circuit for second-order differentiating an output signal outputted from an automatic gain control (AGC) circuit which receives a read signal read from a data recording medium; an arithmetic circuit for determining a time difference between a first intersection Pz0 (Time Tz0) of the output signal and a slicing level, and a second intersection Pz2 (Time Tz2) of the second-order differentiated signal and a zero level; a comparison circuit for comparing the determined time difference with a predetermined time to obtain a comparison value; and means responsive to the comparison circuit for controlling the setting of a rate of convergence for an error between the amplitude of the output signal of the AGC circuit and a predetermine amplitude, and the setting of a rate of convergence for an error between the frequency determined by the period of a time cell defined by a phase-locked loop circuit (PLL) and the frequency of the output signal from the AGC circuit.
A data reproducing method according to the present invention includes the steps of: second-order differentiating an output signal outputted by an AGC circuit; detecting a second intersection Pz2 of the second-order differentiated signal and a zero level; determining a time difference between a first intersection Pz0 of the output signal and a slicing level, and the second intersection Pz2; comparing the determined time difference with a predetermined time to obtain a comparison value; and controlling a rate of convergence for an error between the amplitude of the output signal from the AGC circuit and a predetermined amplitude, and a rate of convergence for an error between the frequency determined by the period of a time cell defined by PLL and the frequency of the output signal from the AGC circuit based on the comparison value.